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DDR RAM Overclocking Terminology FAQ
This Terminology FAQ covers overclocking for DDR RAM for both Intel and AMD platform and adds a reference material for various guides found on hisevilness.com. RAM overclocking can be time-consuming and involves a comprehensive set of knowledge with multiple settings mostly accessible through the motherboard BIOS. As well as some abbreviation you come across when reading up on DDR RAM overclocking.
What is DDR*?
DDR stands for Double Data Rate, and the number represents the version per JEDEC design. A RAM kit advertised speed is the speed in Mhz.
What is XMP?
XMP profile is a unique profile that "overclocks" the RAM sticks above JEDEC spec(2133Mhz). This profile is always safe to use and is within the design spec of a specific DDR revision.
DIMM stands for Dual In-line Memory Module and represent the stick or sticks in a RAM kit. A DIMM slot is a socket that is DDR version-specific in pin layout on the motherboard.
A channel is a direct link from a DIMM slot to the CPU socket and therefor CPU itself. Also known as traces that represent the physical pathway in the motherboard. There are several Channel layouts, Dual-Channel where the CPU can fully utilize RAM sticks in Mhz slotted in at least 2 DIMM slots. Quad Channel usually found on HEDT can fully use minimal 4 RAM sticks in DIMM slots in Mhz. Channels can be shared, but this will sacrifice speed in Mhz and slightly increase latency.
What is an IC?
An IC is the physical silicone on a PCB of the RAM stick that presents the capacity of a RAM stick. Multiple ICs make up the full capacity of the RAM stick and come in single rank(on one side of the PCB) or dual rank(on both sides of the PCB).
IMC stands for Internal Memory Controller and is located inside the CPU in the uncore/SoC domain. And handles communication with the motherboard chip, RAM, PCIe, IO etc.
NS stands for Nano Seconds and is the ability of a RAM kit to send and receive data in nanoseconds. Latency impacts the performance of read, write and copy speeds.
Is a motherboard trace layout that will allow for better 4 DIMM support on dual-channel CPU's. While still sharing one channel for 2 DIMM they are made in such a way that the signal is transmitted equally among both DIMMs.
Is a motherboard trace layout that allows dual-channel support CPUs to share each channel of a total of 4 DIMMs. This trace layout still favours the use of 2 DIMMs since the signal strength most commonly DIMM 2 and 4 is the best.
What are save voltages for DRAM?
Voltages for DRAM according to JEDEC spec should be able to handle up to 1.5v, but this is not the case for specific ICs. While Samsung B-die can handle up to 1.5v the other Brand ICs such as Hynix or even Samsung E-die only can safely handle up to 1.45v. Higher voltages will require direct cooling such as water cooling with B-die over 1.5v and all the other revision of die over 1.45v.
|DRAM Voltage||1.20v ~ 1.45v||1.45v ~ 1.5v|
What are save voltages for DDR VTT/DRAM VTT?
DRAM VTT should not be mistaken for CPU VTT also known as VCCIO. DRAM VTT can help stabilize memory overclocks in combination with DRAM voltage. DRAM VTT should be half the DRAM voltage so as an example an XMP 1.35v DRAM voltage should be 0.675v DRAM VTT.
|DRAM VTT Voltages||1.1v ~ 1.25v||1.25v ~ 1.4v|
procODT is found on AMD Ryzen CPUs. And dictates how a data signal is terminated after it is completed. You want a lower resistance(procODT) with lower memory frequencies and higher resistance(procODT) with higher frequencies. Changing procODT should be done one value higher or lower within the range of the table below.
|Memory Frequency||3200 Mhz and Lower||3200 Mhz - 3600 Mhz||3600 Mhz - 3800Mhz|
|procODT||40 ohm - 48 ohm||48 ohm - 53 ohm||53 ohm - 68 ohm|
CLDO_VPP is the voltage supply for the interface between the CPU IMC and the DRAM Modules. The DDR4 PHY as it is known is part of the SoC domain and translates signals from the IMC to the Memory sticks. The value for CLDO_VPP is in Mv and is limited to 1 volt. Changing this value helps to counter-memory holes and requires a cold reboot if adjusted. Lowering the CLDO_VPP is more common then increasing the CLDO_VPP. Changing this value should be done with care as it is very sensitive. So in short when a VLCO_VDDP value of 850 does not stabilize a memory OC the value should be raised initially by 15 ~ 20 mv to 865 ~ 870.
CLDO_VDDG is a new voltage introduced with the Ryzen 3000 series to help combined with CLDO_VDDP to help with the IMC. However, CLDO_VDDG is specifically for the Infinity Fabrics and is regulated from the SoC power rail. Since CLDO_VDDG is tied to the SoC voltage changing either of these voltages will change the other as they act as a pair. Thus when manually changing CLDO_VDDG and SoC voltages the CLDO_VDDG voltage has to be within ~40mv. Changing CLDO_VDDG does not always help but can help in some scenarios when overclocking the FCLK(Infinity Fabric).
What are save voltages for AMD SoC?
SoC voltage is the same for all architectures with the Ryzen CPUs. And are used when overclocking the FCLK(Infinity Fabric) and MCLK(Memory Frequency). And in some cases can help to stabilize CPU overclocking.
|Ryzen SoC||1.000v ~ 1.150v||1.150 ~ 1.250|
Safe VCCIO and VCCSA voltages have been the same for about a decade and span several Intel nodes. Using extreme voltage could lead to damage of the IMC and motherboard traces.
|VCCIO Voltage||1.10v ~ 1.25v||1.25v ~ 1.35v|
|VCCSA Voltage||1.10v ~ 1.25v||1.25v ~ 1.35v|
The primary timings of a RAM kit are always listed on the sales page and packaging. These numbers indicate the performance ability of a kit to transfer data, delay, pre-charge. The lower the number on the Primary Timings the faster your RAM kit can transfer data. Changing Primary Timings will impact latency and bandwidth. These are easily accessible in various tweaking software as well as in the motherboard BIOS.
Secondary timings are rarely found on marketing material. As with Primary Timings, they indicate the performance ability of the DDR kit to transfer data, delay, pre-charge. Lower Secondary Timings allow your RAM kit to transfer data faster. Changing Secondary Timings will impact latency and bandwidth. And they can be found in the BIOS of most motherboards.
Tertiary Timings are never found and are different per motherboard, CPU and RAM kit of the same manufacture and kit. They require special training from the motherboard, and this is the main reason your PC will reboot a couple of times when you install a new RAM kit. Lower Tertiary Timings impact bandwidth only and only high-end motherboards will allow you to change these timings.
Command Rate is not a timing but is listed in most marketing material and found under Primary Timings. It is accessible in most tweaking software and the BIOS with the Primary Timings. The number indicated the clock cycle needed to send and receive data from the CPU. CR is also known as T or N in the motherboard BIOS. And the number is clock cycle required to CR1 = 1 clock cycle. Changing CR impacts latency and CR1 is preferred over CR2. In contrast, CR1 is harder to overclock but has a 5% performance advantage over CR2. CR3 is commonly seen on HEDT with Quad-Channel.
These are latency settings and not timings and can be found under Tertiary Timings or a separate section in the BIOS of high-end motherboards. Adjusting RTL and IO-L should be done in sync. If not, it will increase latency and impede performance or even cause instability.
What is DRAM Voltage?
Is the voltage supply to your RAM, aka Memory sticks, increasing the DRAM voltage will allow your RAM to run at a higher frequency and tighter timings will increase heat output.
VCCIO voltage needs to be adjusted when increasing the Mhz of the RAM kit. Overshooting VCCIO can lead to instability; thus, it is wise to test the correct voltage since a overclock could be stable, but to high VCCIO voltage is making it unstable. A rule of thumb is that you will need 1.25v or more on overclock that exceed 4000mhz.
VCCSA voltage needs to be adjusted when using tighter timings at relative low memory frequency such as 14-14-14-32 @ 3200mhz. When using higher frequencies VCCSA needs to be modified when attempting to lower the timings, for instance, 17-17-17-34-C2 @ 4000mhz needs more VCCSA then 19-19-19-38-CR2 @ 4000Mhz.
SoC voltage needs to be adjusted with FCLK(Infinity Fabric),MCLK(RAM frequency), and RAM timings. So regardless of changing either of the settings mentioned above, SoC voltage will need to be adjusted.
Enables the memory to run half the average speed generated internally in MHz. Gear Down Mode can be seen as Command Rate 1.5. Enabling Gear Down Mode will prevent you from running Command Rated 2(T2/N2/CR2) and will only allow even tCL .
These common questions barely scratch the surface of DDR RAM overclocking but will help you get started in the future more information will be added, covering more in-depth topics.
- Enjoy overclocking, Paul "HisEvilness" Ripmeester